Abstract
This paper presents improved flip-chip bonding for silicon carbide (SiC) dummy chips with a silicon dioxide (SiO₂) insulation/passivation layer, targeting high-temperature (up to 600 °C) applications in three-dimensional integrated circuit (3D IC) packaging. The SiO2 layer was introduced to mitigate electrical leakage caused by the deposition of conductive metal pads directly on the semiconducting SiC substrate. The SiC wafer with a SiO₂ insulation/passivation layer was fabricated with sputtered Ti/TaSi₂/Pt thin-film conductive pads, while an alumina substrate featured screen-printed gold conductive pads. Two packaging configurations, chip-to-chip (CtC) and chip-to-substrate (CtS), were implemented and compared using an improved thermocompression flip-chip bonding process with parallel alignment prior to bonding. The daisy chain electrical resistance measurements for both configurations showed a similar trend: a sharp decrease during the first 2 days of thermal aging, followed by a gradual reduction and stabilization at approximately 51 Ω for the CtC bonding packages and 19 Ω for the CtS bonding packages. The Die shear tests showed that the shear strength of the packages increased significantly after 2 days of thermal aging, rising from approximately 15 gram force per bump (gf/bump) to about 65 gf /bump and 50 gf /bump for the CtC and the CtS bonding packages, respectively. These results demonstrate that incorporating a SiO₂ insulation/passivation layer and an optimized flip-chip bonding process significantly improves the electrical reliability and the mechanical robustness of high-temperature flip-chip packages.