Abstract
This work studies a 3D stacking approach to silicon carbide (SiC) integrated circuit (IC) chips using flip chip technology with gold stud bumps for high temperature (up to 600°C) applications. Standard photolithography, sputtering deposition, and lift-off process were used for chip metallization and patterning with titanium (Ti), tantalum silicide (TaSi 2 ), platinum (Pt), and gold (Au) thin films. Gold stud bumps were used to bond the SiC dummy chips with a flip chip die bonder. Die shear tests were conducted, and the electric resistance of the daisy chain interconnect between the chips was measured before and after thermal aging in the air at 600°C for up to twelve days. It is found that the electric resistance of the daisy chain interconnects decreases and stabilizes at about 1 Ω for 36 bumps, showing that the thermal aging process improves the electric performance of the interconnect with gold stud bump bonding by reflowing and annealing the metals. The destructive die shear test shows that, with thermal aging, the shear force decreases for the chip stacks and stabilizes at about 15-gram force (gf) per bump with TaSi 2 diffusion barrier in the metallization. In contrast, the shear strength increases for the chip stacks without TaSi 2 barrier in the metallization.