Abstract
This paper presents the design of a high-precision, low-voltage inverter-based comparator. The comparator employs current-limiting and current calibration circuits to reduce power consumption and improve precision by correcting the errors associated with the inaccurate reset operation of the comparator. An analytical model was developed to determine the optimum operating point for the voltage gain and the effects of reset operation on the characteristics of the comparator. The model was verified through simulations using the TSMC 0.18-μ m N-well CMOS process and was used to develop current-mode calibration and power-reduction techniques to improve the gain of the comparator. The simulations showed an improvement in the gain by a factor of 3 x with minimal added power consumption. Monte Carlo and process corner simulations were performed to verify the effectiveness of the proposed calibration technique. A 5-bit flash and 12-bit SAR analog-to-digital converters (ADCs) were designed using the new comparator and calibration technique as a proof of concept to demonstrate the superiority of the calibration technique, which significantly improved the resolution of the ADC. Thus, it was concluded that the proposed current-limited current-calibrated (CLCC) inverter-based comparator can be used in high-precision, low-voltage data converters in applications where resolution and supply voltage are critical design considerations.