Abstract
Silicon carbide integrated circuits (SiC ICs) have been demonstrated to operate at high temperatures, such as ~460 °C at the Venus' surface, for two months, and for over a year at 500 °C. At these high temperatures, the SiC integrated circuits and sensors need to be packaged in quite different ways than those below 300 °C. In addition, to integrate more devices into the limited footprint of the high-temperature circuit board, three-dimensional (3-D) packaging is a notable advantage. In this work, 3-D stacking of SiC chips using a gold wirebonding interconnect is investigated. The gold bonding wire is used due to its mechanical robustness and chemical inertness at high temperatures. Triple-stacked SiC chips are bonded to each other and to the gold conduction pads on the alumina substrate with screen-printed gold pastes. The mechanical die shear test, wire pull tests, and interconnect electrical resistance tests are executed and analyzed before and after the 3-D SiC chip packages are subject to a 600 °C thermal aging process in the air for up to 10 days. This 3-D SiC chip packaging has promise for long-duration high-temperatures (up to 600 °C) applications and may be potential for use for applications such as Venus's surface sensing and telemetry.