Abstract
The size of field effect transistors used in CMOS integrated circuits shrinks over each technology node to achieve lower power consumption, higher performance, and higher density. The increase in electrostatic control and reduced short channel effects (SCE) are key benefits to adopting new architectures like Gate-All-Around FET (GAAFET) to meet scaling requirements for next generation process nodes. Advanced architectures in the nanometer regime bring unique design challenges that require thorough characterization of device performance to ensure a successful and robust implementation. Sentaurus TCAD provides a valuable tool to begin exploring the many design choices faced when encountering a novel structure such as GAAFET. Design choices around device geometries and materials can be simulated to understand impacts on performance. In this work, several of these design choices are explored, such as channel geometry, vertical channel stacking, and spacer material options, all while using the projected parameters of the 2nm node. Key device metrics like transfer characteristics, SCE, extension resistance, and gate capacitances are used to create a basis for evaluating the design health. The devices designed using TCAD are then simulated at the circuit level to further explore tradeoffs and provide additional figure of merits into device performance.