Abstract
A massive number of images and videos are captured by mobile phone cameras every day. Thus, the built-in cameras become essential in almost all produced mobile phones and devices. To compete, device manufacturers improve image sensors’ performance in camera modules and optimize it for high frame rate, better image quality, low power consumption, low cost, and added features.Solid-state image sensor is the core of today’s camera systems. Two well-known technologies exist for image sensors, which are the charge-coupled devices (CCD) and complementary metal-oxide-semiconductor (CMOS) image sensors (CIS). CCD was the dominant and mature technology for a long time until CIS appears in the early 1990s to solve CCD drawbacks. CIS has several crucial advantages over CCD, including integrating peripheral circuits on the same chip, minimizing overall system size, and forming a camera system-on-chip (SOC). Besides other advantages, just these advantages of CIS have qualified it to be integrated with the modern mobile phone systems.
Typically, the built-in camera module’s power consumption specification is crucial for mobile devices’ overall battery life. Besides low-power consumption, image sensors in these camera modules require high-resolution and high-quality image reproduction capabilities to provide a competitive edge for the manufacturers to dominate in the marketplace. Today, CIS is the technology of choice due to its low-power consumption, high resolution, and increased integration capabilities. One of the essential blocks in the CIS that affects its speed, power consumption, image quality, and resolution at the same time is the analog-to-digital converter (ADC). Thus, optimizing and improving the performance of integrated ADCs is crucial for CIS performance. Many ADC types have been used in CIS. One of the most efficient types is the integrating (ramp) type ADCs, as they are small, easy to integrate, consume minimal power, and fulfill high-resolution requirements easily while providing low-noise operation. However, they suffer from the conversion speed problem when bit resolution is increased. Many solutions were proposed to improve the conversion speed of ramp ADCs in CISs while maintaining acceptable bit resolution and, consequently, reproduced image resolution and quality at the same time.
In this research, two speedup techniques (SuPTs) are proposed to improve the conversion speed of ramp-type ADCs integrated with a CIS column-parallel architecture (CPA). They are the single-slope look-ahead ramp (SSLAR) and accelerated single-slope look-ahead ramp (ASSLAR) ADCs. Measurements of the SSLAR SuPT in a 200 × 150 pixel CIS chip showed that a 6x frame rate increase could be achieved while reducing power consumption 13% without compromising image quality. The ASSLAR SuPT, on the other hand, improved the performance of the SSLAR and the well-know accelerated ramp (AR) SuPT by enhancing the speedup ratio (SuPR) by 20% on average while keeping the structural similarity of the reproduced image not affected by the proposed algorithm and structural similarity index of over 98%.
These new CIS SuPTs have some inherent settings that control speed-up ratio (SuPR) and ADC bit-resolution. As a result, power consumption, frame rate, and image quality of the CIS can intelligently be controlled and optimized. This intelligent control requires predicting the content and complexity of captured scenes without requiring complex computational resources. To do this, a new image quality (IQ) metric, called conversion complexity metric (CCM), was developed to simply and quantitatively measure complexity for any scene captured by CIS or a still image stored on a medium. It provides an index number for smart adjustment of the performance parameters of CIS electronics, including on-chip ADCs. The CCM was proven to be bounded, monotonic, 99% linear, and 316% sensitive. It is a computationally efficient single-image quality metric that no other metrics could provide for CIS to intelligently adjust and optimize on-chip analog and digital signal processing operations. The new CCM can also be used for comparing different SuPT for different ramp ADCs used in CIS CPAs.
A new image quality and complexity comparison methodology is also proposed based on the CCM index and existing image quality metric, known as structural similarity metric (SSIM). This new methodology is proposed to set up a fair comparison between different SuPTs. Each SuPT has its controlling parameters (CPs) to adjust SuPR while trading off some CIS performance parameters, such as reproduced image quality of which, if not considered during the comparison procedure, it may result in a misleading performance advantage. Using the proposed comparison methodology guarantees that a fair comparison and judgment of different SuPTs is possible. A case study was developed to apply this new comparison methodology to compare the new ASSLAR and the existing AR SuPTs. This case study resulted in a process to hybridize these two powerful SuPTs to get superior performance. It was found that for the highly complex images with a CCM index of 0.5 or lower, the AR SuPT has to be used. For less complex images with a CCM value of 0.5 or more, it is beneficial to use the proposed ASSLAR SuPT to provide 20% or more SuPR compared with AR SuPT in CIS CPA.