Abstract
This dissertation presents the development of high-gain, low-noise, and scalable readout integrated circuit (ROIC) electronics for CMOS image sensors (CIS), with a particular focus on improving performance for low-light and single-photon imaging applications. Low-light performance of image sensors can be enhanced by designing pixel readout signal chain to have high effective conversion gain. This can be achieved by using high-gain in-pixel amplifiers. High-gain amplifiers can be realized using differential or single stage amplifiers in negative feedback configurations (closed loop) in each pixel. However, this leads to very large pixel sizes along with huge power consumption for the image sensor. In this study, an open-loop, high-gain common-source (CS) amplifier, and associate biasing and readout techniques, called the source modulation (SMOD) and current modulation (CMOD), are proposed that can be integrated in the readout signal chain of complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS) imagers.The CS amplifier typically suffers from a limited input range and non-linear gain, making it challenging to employ as an in-pixel amplifier. To maintain high gain biasing and to mitigate non-linear input-output (IO) characteristics, a novel design technique, called SMOD, is introduced. The SMOD technique utilizes a modulation scheme for adjusting the bias point of the CS amplifier, leveraging the shift in the input-output transfer characteristic which occurs when the source voltage is modulated. By exploiting this shift, the amplifier’s optimal biasing and gain can be restored, thereby enhancing the pixel’s effective conversion gain. A comprehensive analysis of the input-output behavior of the proposed in-pixel CS amplifier, along with the associated modulation methods, are presented.
Another technique to achieving in-pixel high-gain amplification was developed through using gate modulation (GMOD) technique for a transconductance amplifier. To validate, a continuous-time/current-mode CIS was designed and fabricated instead of the conventional integration-type/voltage-mode imager. Various techniques were employed to reduce the noise of the readout signal chain and to enhance the signal-to-noise ratio (SNR) of the CIS.
Additionally, a high-precision/high-speed inverter-based comparator was developed for use in analog-to-digital converters (ADCs) for high-speed CMOS image sensors. The comparator employs a novel current modulation (CMOD) technique for calibration to improve its noise performance and minimize the metastability range by maintaining its amplifier’s (the inverter) biasing at its maximum gain operating point. This design enables more reliable and faster decision-making, which is critical for achieving high-resolution and low-noise integrated ADCs in CIS readout signal chains.