Abstract
Ultra-wideband (UWB) communications and software defined radio (SDR) have been widely researched topics for the past several years. This is mainly because of the increased demand for robust, multi-purpose, and reconfigurable high data rate wireless communication systems with low energy consumption. Moreover, limited availability of RF spectrum bands for commercial use and variations of them from one country to another demand the wireless-capable devices to have greater re-configurability. Therefore, the communication systems of the future will not only have to allow multiple application usage, but also properly operate in a variety of environments with many other communication systems. Applications of these technologies range from short range battlefield military communication, interoperability of different radio signals, and wireless indoor data transfer and connectivity, to wireless sensor networks that require continuous data transmission.
High-speed, medium resolution (5-8bits), and low-power analog-to-digital converters (ADCs) are essential components of most high data transfer rate communication systems. In UWB systems, as well as digital oscilloscopes, SDRs, and many other high speed communication applications, the speed and resolution of the ADC blocks limit communication systems from covering wide frequency bands. The intent of the work presented in this dissertation is to review and disclose the research findings on novel analog-to-digital converter structures designed for high-speed medium to high resolution, and re-configurable structures for UWB and SDR applications.
The technical inquiry is divided into four research objectives. The first objective is to investigate fundamental principles, architectures, and transistor-circuit-system level limitations and design challenges of available state of the art ADC topologies for UWB and SDR applications. The second objective is to develop novel ADC topologies by utilizing asynchronous signal processing functionalities and by using hybrid structures to overcome the architecture level limits. The third objective is to study the main causes of high-speed ADC imperfections and develop novel correction techniques to achieve better performance. The fourth objective is to realize those novel ADC structures and the correction techniques on silicon and compare actual measurements with the simulation results as a proof of concept.
The research outcomes include: (1) understanding the challenges of high-speed ADC design, (2) understanding the challenges in the design of flexible ADC architectures that can easily be re-configured between high data rate-medium resolution and low data rate-high resolution operations, (3) understanding the impact of circuits non-idealities on the overall ADC performance, and the different techniques used to reduce them, (4) developing novel and efficient techniques to correct for the top contributors of the circuits non-idealities, and (5) developing novel ADC architectures that can fulfill the requirements of UWB and SDR systems.
The intellectual merits include: Two asynchronous time-interleaved (TI) type ADC architectures and a novel and efficient offset correction technique targeting set goals of the research are reported in this dissertation. The novel coarse-fine-calibration (CFC) offset correction technique was developed for increasing the accuracy of comparators used in ADCs while maintaining small area and power consumption for correction circuits.
Major contributions of this research are: (1) design of a novel offset correction technique for dynamic latched comparators that are the key blocks in most ADC topologies to improve its sampling speed and the bit resolution, (2) design of a new asynchronous successive approximation register (ASAR) ADC in a time-interleaved structure, (3) design of a novel asynchronous two bit per stage, binary search ADC with indirect reference switching (ABS-IRS) in a time-interleaved structure, and (4) design, implementation, and testing of the three structures on silicon.