Abstract
The hardware-level security schemes necessitated in cutting-edge embedded and heterogeneous computing systems (such as Microsoft Catapult [8]), especially encryption metadata access and authentication can incur up to 14x reduction in critical system throughput [17]. In this paper, we present CTR+, a novel method to access encryption metadata for secure embedded memory, allowing for parallel speculative use of metadata (encryption counters) for encryption/decryption purposes during active authentication process to reduce the integrity verification overhead. This scheme utilizes a metadata cache with speculative queue in the presence of a pipelined integrity tree controller and elevates the performance by up to 67% against a baseline and up to 32% when compared to a state-of-the-art solution in memory-intensive applications.